1. Field of the Invention
The invention relates generally to the testing of electronic circuits, and more particularly to systems and methods for controlling the execution of LBIST test cycles to allow identification of errors in bit patterns produced by the functional logic of a device under test.
2. Related Art
Digital devices are becoming increasingly complex. As the complexity of these devices increases, there are more and more chances for defects that may impair or impede proper operation of the devices. The testing of these devices is therefore becoming increasingly important.
Testing of a device may be important at various stages, including in the design of the device, in the manufacturing of the device, and in the operation of the device. Testing at the design stage ensures that the design is conceptually sound. Testing during the manufacturing stage may be performed to ensure that the timing, proper operation and performance of the device are as expected. Finally, after the device is manufactured, it may be necessary to test the device at normal operating speeds to ensure that it continues to operate properly during normal usage.
One way to test for defects in a logic circuit is to use a non-deterministic approach in which pseudorandom input test patterns are applied to the inputs of the logic circuit. The outputs of the logic circuit are then compared to the outputs generated in response to the same pseudorandom input test patterns by a logic circuit that is known to operate properly. If the outputs are the same, there is a high probability that the logic circuit being tested also operates properly. The more input test patterns that are applied to the logic circuits, and the more random the input test patterns, the greater the probability that the logic circuit under test will operate properly in response to any given input pattern.
One test mechanism that can be used to implement a non-deterministic testing approach is a built-in self test (BIST). This may also be referred to as a logic built-in self test (LBIST) when applied to logic circuits. BIST and LBIST methodologies are part of a group of methodologies referred to as design-for-test (DFT) methodologies. DFT methodologies impact the actual designs of the circuits that are to be tested. LBIST methodologies in particular involve incorporating circuit components into the design of the circuit to be tested, where the additional circuit components are used for purposes of testing the operation of the circuit's logic gates.
In a typical LBIST system, LBIST circuitry within a device under test includes a plurality of scan chains interposed between levels of the functional logic of the device. Typically, pseudorandom patterns of bits are generated and stored in the scan chains. This may be referred to as scanning the data into the scan chains. After a pseudorandom bit pattern is scanned into a scan chain, the data is propagated through the functional logic to a subsequent scan chain. The data is then scanned output of the subsequent scan chain and accumulated to form a single LBIST signature. This test cycle is typically repeated many times (e.g., 10,000 iterations,) with the results of each test cycle being accumulated into the LBIST signature. After all of the scheduled test cycles have been completed, the LBIST signature is compared to an LBIST signature generated by a device that is known to operate properly. Based upon this comparison, it is determined whether the device under test operated properly.
While conventional LBIST implementations are useful to determine whether the device under test operated properly (and can therefore be expected to continue to operate properly,) they typically are not very useful to determine the source of an error that occurs during the test. Because many test cycles are executed and their results accumulated into a single LBIST signature prior to comparison of the signatures of the device under test and the good device, the sources of errors cannot be localized. In more recent LBIST systems, it may be possible to compare LBIST signatures after each test cycle to determine at which test cycle the error occurs.
Even if the LBIST system is capable of stepping through each test cycle, this only identifies the particular test cycle at which the error occurred. There may be many scan chains, each of which includes many more scan latches. The data from all of these scan latches is combined into the LBIST signature at the end of the test cycle, so the signature can indicate that an error has occurred, but not the source of the error.
Another shortcoming of this test-cycle-by-test-cycle approach is that it does not detect some errors. Some errors are dependent, not only upon the specific input bit pattern that is propagated through the functional logic of the device under test, but also upon the history of operation just prior to propagating this bit pattern through the functional logic. For example, a particular sequence of bit patterns may cause the device to experience a very large change in current (large dI/dt,) which may cause the functional logic to behave in a manner which is unexpected. While the execution of the LBIST test at speed may cause the device to experience an error, performing the LBIST test in a step-by-step fashion may actually reduce the magnitude of the change in current, thereby avoiding the error.
It would therefore be desirable to provide systems and methods for performing LBIST testing that enable the identification of these types of errors that appear in at-speed LBIST testing, but not step-by-step testing, and allow localization of the errors to the test cycles in which they occur and examination of the bit patterns in the scan chains to identify the sources of the errors.